Tsmc Unveils Ambitious 3D Stacking Plan To Fuel Next Gen Computing

TSMC’s 3D Stacking Roadmap: A Critical Component in the Quest for Enhanced Compute Density and Performance

The world of semiconductor manufacturing is witnessing a significant transformation with the advent of cutting-edge technologies that enable the creation of ultra-compact, high-performance computing systems. At the forefront of this revolution is TSMC (Taiwan Semiconductor Manufacturing Company), which has been working tirelessly to develop its System-on Integrated Chips (SoIC) technology with 3D interconnects.

TSMC’s SoIC technology has undergone a significant evolution, with its first-generation design supporting face-to-back (F2B) stacking but not face-to-face (F2F) stacking. The introduction of the second-generation SoIC technology addressed this limitation by enabling F2F stacking, which offers several advantages over traditional F2B configurations.

Face-to-back stacking imposes fundamental limits due to the indirect signal path required between dies. This results in increased latency, power consumption, and routing complexity. In contrast, face-to-face stacking enables direct metal-layer alignment, eliminating the need for TSVs (silicon vias) and significantly increasing signal density by an order of magnitude.

The adoption of F2F stacking technology has a profound impact on compute density and performance. With straight, ultra-short vertical interconnects enabled by hybrid copper bonding, communication between stacked dies resembles on-die wiring rather than chip-to-chip links. This results in increased bandwidth, reduced latency, and lower energy usage per bit.

The use of F2F stacking technology is particularly beneficial for AI and HPC processors that require massive amounts of cache to maximize single-thread performance relatively cost-efficiently. By leveraging N2-based CPU chiplets atop N5-made SRAM chiplets, Broadcom and Fujitsu were able to achieve significant gains in performance while maintaining manageable complexity.

Fujitsu’s Monaka supercomputer CPU is a prime example of the benefits that F2F stacking technology offers. With 144 Armv9 cores spread across four compute chiplets, Monaka integrates a stacked face-to-face (F2F) atop dedicated SRAM chiplets using hybrid copper bonding. This innovative design enables Broadcom and Fujitsu to add massive amounts of cache to Armv9 cores while maintaining relatively low complexity.

The adoption of F2F stacking technology by industry leaders like Broadcom is expected to accelerate the development and deployment of this critical component in the quest for enhanced compute density and performance. As TSMC continues to push the boundaries of its SoIC technology, it is clear that 3D stacking will play a vital role in shaping the future of computing.

The roadmap revealed by TSMC outlines an aggressive development timeline for its 3D stacking SoIC technology. With current 6-micron pitches expected to decrease to 4.5 µm by 2029, TSMC is poised to revolutionize the computing landscape. Kevin Zhang, TSMC’s Senior Vice President of Business Development and Global Sales, reassured that the company will support 3D integration even with backside power delivery.

The SoIC roadmap shown does not cover all possible combinations, but two key takeaways emerge: pitch scaling and the acceleration of stacking timelines. The introduction of A16 nodes is expected to build upon the successes of N2P on top of N3P, while N2P on top of N2P by 2028 promises significant further advancements. The eventual goal is to achieve 3D stacked A14 dies by 2029, a testament to TSMC’s commitment to innovation and its determination to push the boundaries of what is possible in computing.

The adoption of 3D stacking technology offers immense opportunities for enhancing compute density and performance. As transistor scaling slows down, packaging has become the inevitable scaling engine. With TSMC poised to revolutionize the computing landscape, industry leaders are expected to increasingly adopt this critical component.

In conclusion, TSMC’s 3D stacking roadmap represents a significant development in the quest for enhanced compute density and performance. By pushing the boundaries of its SoIC technology, TSMC is poised to redefine the computing landscape, offering unparalleled opportunities for innovation and growth. As the semiconductor industry continues to evolve, it is clear that 3D stacking will play an increasingly vital role in shaping the future of computing.

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