Revolutionary Chip Scaling Achieved: Ibm Lams Push Boundaries To 1Nm With Historic Collaboration

IBM and Lam Research have announced a groundbreaking collaboration to develop the materials and fabrication processes needed for high-NA EUV lithography and Lam’s Aether dry resist technology. The partnership will take place at IBM Research’s state-of-the-art facilities at the NY Creates Albany NanoTech Complex in Albany, New York.

The two companies have a long history of collaboration, having worked together for over a decade to advance the field of nanotechnology. Their previous efforts have led to significant breakthroughs in 7nm process development, nanosheet transistor architecture, and early EUV process integration. In 2021, IBM unveiled what it described as the world’s first 2nm node chip.

Under the new agreement, the focus will shift to validating full process flows for nanosheet and nanostack device architectures, utilizing Lam’s cutting-edge Kiyo and Akara etch platforms, Striker and ALTUS Halo deposition systems, and Aether dry resist. This comprehensive approach aims to enable high-NA EUV patterns to be reliably transferred into real device layers with high yield.

Conventional EUV lithography relies on chemically amplified resists, wet-process materials that struggle with the tighter tolerances demanded by high-NA EUV scanners. In contrast, Lam’s Aether technology is a dry resist, deposited via vapor-phase precursors rather than spin-coating, and developed using plasma-based dry processes.

Aether’s metal-organic compounds absorb three to five times more EUV light than traditional carbon-based resist materials, which significantly reduces the dose required for each wafer pass. This not only saves time but also minimizes the risk of pattern degradation at tight geometries. By leveraging Aether’s superior properties, Lam aims to accelerate industry adoption of High NA EUV for next-generation interconnect and device patterning.

One of the key challenges in high-NA EUV lithography is maintaining single-print patterning at advanced nodes without resorting to more expensive multi-patterning techniques. This is where Lam’s Aether dry resist technology shines, as it reduces the number of steps between exposure and etch, minimizing opportunities for pattern degradation.

The team will build and validate full process flows for both nanosheet and nanostack devices, alongside backside power delivery, which routes power through the back of the wafer to free up front-side interconnect layers for signal routing. To achieve reliable transfer of high-NA EUV patterns into real device layers with high yield.

The IBM-Lam partnership is a testament to the power of collaboration between industry leaders and researchers. By pooling their expertise and resources, these two companies are pushing the boundaries of what is possible in chip scaling and lithography. As we move forward in an increasingly complex technological landscape, partnerships like this one will be crucial in driving innovation and progress.

In conclusion, the IBM-Lam partnership on high-NA EUV dry resist technology represents a significant milestone in the quest for smaller, faster, and more efficient electronics. By leveraging Lam’s Aether dry resist technology and IBM’s expertise in nanotechnology, the team is poised to achieve reliable transfer of high-NA EUV patterns into real device layers with high yield.

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